Job Description

ASIC Design Verification Engineer – Bay area #8012

My client is a very promising well-funded startup at the cutting edge of integrating LLMs with chip design. Their team is composed of experts in the fields of AI, software development, and semiconductor design. The founders have an amazing background and pedigree, perfect for this venture. This totally new approach to chip design is a game changer and with their strong foundation and existing customer base, they are positioned to redefine the landscape of chip design.

Job Description:

They are looking for skilled and passionate Chip Designers or Verification Engineers who have significant experience with VLSI front-end design flows to collaborate closely with their ML and software teams. In this unique role, you will apply LLM’s for DV; you will work on advanced technologies that leverage your design verification experience with ML for innovative chip design solutions; You will have the opportunity to learn from experienced ML leads and directly contribute to projects for their existing customers.

This position is ideal for a chip designer who is eager to push beyond traditional roles and explore the frontier of AI-integrated semiconductor design. This terrific opportunity will give you the opportunity to make a real and significant contribution, as they unleash this existing, yet totally new approach to CHIP DESIGN.

Key Responsibilities:

• Collaborate with ML and software teams to develop advanced, AI-driven chip design solutions.
• Work with customers to best understand their needs with the team
• Learn from and work closely with strong ML leads to understand and implement cutting-edge technologies in chip design.
• Engage directly with customer projects, applying your expertise to develop practical and innovative solutions.
• Contribute to the integration of LLM technologies into the chip design process, enhancing design efficiency and performance.
• Stay updated with the latest advancements in chip design and AI/ML technologies to continually improve methodologies and solutions.

Qualifications:

• A thorough understanding of Formal, Simulation, UVM and similar
• Knowledge in Verification and writing FORMAL and running it for design
• Strong experience in chip design, including a thorough understanding of design verification.
• Solid programming skills (e.g., Python, C/C++, Verilog, SystemVerilog).
• Experience or interest in AI/ML technologies, especially in the context of LLMs, is highly desirable.
• Strong problem-solving abilities and a proactive attitude toward learning and innovation.
• Excellent communication skills and the ability to work effectively in a team-oriented environment.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Good to know

• Proficiency in UVM (Universal Verification Methodology) and/or other verification methodologies.
• Software skills with industry Verification tools

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